HDLBit(1)：Getting Started

设计电路需要的一系列步骤：

1. Writing Code
2. Compiling (Logic Synthesis)
3. Simulation
4. Final Status
5. Problem Statement

写Verilog HDL、VHDL代码，编译代码并生成电路,仿真电路最后解决错误。

Step One

Build a circuit with no inputs and one output. That output should always drive 1 (or logic high).
设计一个电路没有输入和一个输出。并且输出应该总是为逻辑高电平。

module top_module( output one );
    assign one = 1'b1;
endmodule

Zero

Build a circuit with no inputs and one output that outputs a constant 0.

module top_module(
    output zero
);// Module body starts after semicolon

assign zero = 1'b0;
endmodule