FPGA时钟之gated-clk设计

Gated Clock

ASIC designs typically gate clocks to conserve power, with custom clock trees defined for each individual tree. 

The solution is to separate the gating from the clock inputs, and combine individual clocks trees on the dedicated FPGA global clock trees. The software logically separates the gating from the clock and routes the gating to the

clock enables on the sequential devices, using the programmable routing resources of the FPGA.

使用synplify的Specifying Design-Level Optimizations选项fixed gated clock会将clk端的gated逻辑综合至D触发器的CE端，减少clk tree的延时，避免导致不必要的timing问题。

Gated Clock Correct Logic Format
Specifically, the combinational logic for the gated clock must satisfy the following two conditions to have the correct format:
• For at least one set of gating input values, the value output for the gated clock must be constant and not change as the base clock changes.

• For at least one value of the base clock, changes in the gating input must not change the value output for the gated clock.

举例（APB设备的寄存器gated clock设计）

用下降沿pclk将其gating signal 锁存一拍，然后用锁存后的信号与时钟进行AND逻辑，从而达到gated clock的效果。这样在每次配置寄存器时才会有时钟使能，否则pclkg停钟，从而达到省电的目的。

	//generate APB register gated clock
	assign apb_wr = psel && pwrite && (!penable) ; 
	always @(negedge pclk or negedge preset_n) begin
		if (!preset_n)
			apb_wr_reg <= 1'b0;
		else
			apb_wr_reg <= apb_wr;
	end
	assign pclkg = apb_wr_reg & pclk;  //pclkg is register clk

如图所示，在fixed gated clock之前，apb_wr_reg和pclk的与操作输出会直接作为后续寄存的C输入，会引入较大的时钟延时。

在加入fixed gated clock之后，gated逻辑会在D触发器的CE端，而D触发器的C端会是干净的pclk.

如图所示，C1，C2为同一时钟的不同gated clk信号，当C1和C2的gated_clk约束未成功时，可能导致LUT4_FFB3组合逻辑输出的glitch被C2采到，导致i_wdog_res输出错误。