2022校招 加特兰微电子-数字电路设计工程师 (持续更新...)

文章目录

• • • 【问答 | 5分】
    • 【问答 | 10分】
    • 【问答 | 15分】
    • 【问答 | 20分】

【问答 | 5分】

1. What is the difference between blocking and nonblocking assignments?

2. Explain setup failture and hole failture to a flip-flop.

3. What is the difference between clock skew and clock jitter?

4. What is metastability?How to avoid metastability?

5. How to synchronize signals between 2 clock domains?

6. What is the output of the codes below?

module quest_for_out();
	integer i;
	reg clk;
	
	initial begin
		clk = 0;
		#4 $finish;
	end
	
	always #1 clk =! clk;
	
	always @ (posedge clk) begin : FOR_OUT
		for (i=0;i<8;i=i+1) begin
			if(i==5) begin
				disable FOR_OUT;
			end
			$display ("Current i : %g",i);
		end
	end
endmodule

【问答 | 10分】

7. What is the race and hazard? Analyze producing mechanism, and give some general solution measures.

        

8. Implement gate level circuit(AND4，AND2，OR2，INV，etc) according to the following Verilog code.

		assign out = (a[3:0] != 4'b1010);

【问答 | 15分】

9. Implement the edges detection module. This module shall detect rising edge, falling edge and rising or falling edge. (input: clk, rstn, dat_i; output: edge_rising, edge_falling, edge_both)

10. Implement divide-by-3 frequency divider with 50% duty cycle. (input: clk, rstn; output: clk_div)

【问答 | 20分】

11. Implement FSM by the following state transition diagram. (input: clk, rstn, dat_i; output: dat_o)