[SV]SystemVerilog中的基本邏輯與運算 --- （==與===的區別/posedge與negedge是怎麼定義的？）

                  SystemVerilog中的基本邏輯與運算

                                --- ==與===的區別/posedge與negedge是怎麼定義的

 

一、 ==與===的區別

 1.1、先看下面的例子

module equal_test();

  logic    a = 1'bx;
  logic    b = 1'bx;
  logic    c = 1'bz;
  logic    d = 1'bz;

  initial begin
    if(a === b)    $display("a === b; pass");
    else           $display("a === b; fail");

    if(c === d)    $display("c === d; pass");
    else           $display("c === d; fail");  
  end

  initial begin
    if(a == b)    $display("a == b; pass");
    else          $display("a == b; fail");

    if(c == d)    $display("c == d; pass");
    else          $display("c == d; fail");  
  end

  initial begin
    if(a === 1'b1)    $display("a === 1'b1; pass");
    else              $display("a === 1'b1; fail");

    if(c === 1'b0)    $display("c === 1'b0; pass");
    else              $display("c === 1'b0; fail");  
  end

  initial begin
    if(a == 1'b1)    $display("a == 1'b1; pass");
    else             $display("a == 1'b1; fail");

    if(c == 1'b0)    $display("c == 1'b0; pass");
    else             $display("c == 1'b0; fail");  
  end

endmodule : equal_test

• Simulation Output

a === b pass
c === d pass
a == b fail
c == d fail
a === 1 fail
c === 0 fail
a == 1 fail
c == 0 fail

 1.2、結論

• ==在遇到x和z時失效，不能進行比較運算
• ===可以對x和z進行比較
• 在設計Interface的讀取和比較時，建議採用===
• 與===對應的不等號是!==
• 與==對應的不等號是!=

 

二、posedge與negedge的定義

 2.1、見下表

FROM	TO
	0	1	x	z
0	-	posedge	posedge	posedge
1	negdege	-	negdege	negdege
x	negdege	posedge	-	-
z	negdege	posedge	-	-

 

三、Arithmetic operators defined in SystemVerilog

No.	Operation	Meaning
1	a + b	a plus b
2	a - b	a minus b
3	a * b	a multiplied by b (or a times b)
4	a / b	a divided by b
5	a % b	a modulo b
6	a ** b	a to the power of b