全志R11处理器参数详细说明

r11代表了allwinner在智能硬件处理器上的最新成就，它集成了一个以1.2ghz的速度工作的单arm cortextm-a7 cpu，并支持多个外围设备。

cpu

arm cortextm-a7 mp1 processor 
thumb-2 technology 
supports neon advanced simd(single instruction multiple data) instruction for acceleration of media and signal processing functions 
supports large physical address extensions(lpae) 
vfpv4 floating point unit 
32kb l1 instruction cache and 32kb l1 data cache 
128kb l2 cache

memory subsystem 
boot rom

internal on-chip memory 
supports system boot from the following devices: 
- spi nor flash 
- spi nand flash 
- sd/tf card 
- emmc 
supports system code download through usb otg

sdram

internal on-chip memory 
built-in ddr2 in the r11 
clock frequency up to 400mhz 
supports memory dynamic frequency scale(mdfs)

sd/mmc

external off-chip memory and storage device 
two sd/mmc controllers 
1/4-bit data bus 
complies with emmc standard specification v4.41, sd physical layer specification v2.0, sdio card specification

supports hardware crc generation and error detection 
block size from 1 to 65535 bytes

system peripheral 
timer

three on-chip timers with interrupt-based operation 
one watchdog to generate reset signal or interrupt 
33 bits audio/video sync(avs) counter 
24mhz or internal osc clock input

high speed timer

up to two high speed timers 
counters up to 56 bits 
clock source is synchronized with ahb1 clock, much more accurate than other timers

gic

supports 16 software generated interrupts(sgis), 16 private peripheral interrupts(ppis) and 125 shared peripheral 
interrupts(spis)

dma

up to 8-channel dma 
flexible data width of 8/16/32 bits 
supports linear and io address modes 
supports data transfer types with memory-to-memory, memory-to-peripheral, peripheral-to-memory

ccu

9 plls 
one on-chip rc oscillator 
one 24mhz external oscillator 
one 32.768khz external oscillator 
clock management: clock gating ,clock enabling to the device modules, clock reset, clock generation, clock division

pwm

two pwm channels 
supports outputting two kinds of waveform: continuous waveform and pulse waveform 
0% to 100% adjustable duty cycle 
up to 24mhz output frequency

rtc

time,calendar 
counters second,minutes,hours,day,week,month and year with leap year generator 
alarm:general alarm and weekly alarm

lradc

6-bit resolution 
supports hold key and continuous key 
supports single key, normal key and continuous key

crypto engine

supports aes 128/192/256-bit with ecb,cbc,cts,ctr mode 
supports des/tdes with ecb,cbc,ctr mode 
supports sha1 and md5 
160-bit hardware prng with 175-bit seed

display subsystem 
de2.0

output size up to 1024x1024 
supports three alpha blending channel for main display 
supports four overlay layers in each channel, and has a independent scale 
supports potter-duff compatible blending operation 
supports input format yuv422/yuv420/yuv411/argb8888/xrgb8888/rgb888/argb4444/argb1555/rgb565

display output

supports lvds interface with single link, up to 1024x768@60fps 
supports rgb interface with de/sync mode, up to 1024x768@60fps 
supports serial rgb/dummy rgb/ccir656 interface, up to 800x480@60fps 
supports i80 interface with 18/16/9/8 bit, support te, up to 800x480@60fps 
supports pixel format: rgb888, rgb666 and rgb565 
dither function from rgb666/rgb565 to rgb888 
gamma correction with r/g/b channel independence

video engine 
video decoding

supports video decoder for h.264 and jpeg/mjpeg 
supports h.264 bp/mp/hp up to 1080p@30fps 
supports h.264 output formats :nv21,nv12,yu12,yv12 
supports jpeg/mjpeg up to 1080p@30fps

video encoding

supports h.264 video encoding up to 720p@60fps 
jpeg baseline: picture size up to 8192x8192 
supports input picture size up to 4800x4800 
supports input format: yu12/yv12/nv12/nv21/yuyv/yvyu/uyvy/vyuy 
supports alpha blending 
supports thumb generation 
supports 4x2 scaling ratio: from 1/16 to 64 arbitrary non-integer ratio 
supports rotated input

image subsystem 
image input

supports 8/10-bit cmos sensor parallel interface 
supports 8-bit ccir656 protocol for ntsc and pal 
supports itu-r bt 1120 protocol for hd-cif system 
supports 16-bit interface with separate syncs 
mipi-csi2 interface compliant with mipi-dphy v1.0 and mipi-csi2 v1.0 
supports mipi-csi2 1/2 data lanes configuration 
supports format:

- yuv422-8/10 bits 
- yuv420-8/10 bits(for mipi-csi2 only) 
- raw-8/10 bits 
- rgb888/rgb565(for mipi-csi2 only)

performance: 
- still capture resolution up to 5m with parallel interface 
- video capture resolution up to 1080p@30fps with parallel interface 
- still capture resolution up to 5m with mipi-csi2 interface 
- video capture resolution up to 1080p@30fps with mipi-csi2 interface 
- mipi-dphy maximum data rate up to 1gbps per lane

isp

supports input formats:8/10-bit raw rgb,8-bit ycbcr 
supports output formats: ycbcr420 semi-planar,ycrcb420 semi-planar, ycbcr422 semi-planar,ycrcb422 semi-planar,yuv420 planar,yuv422 planar 
supports image mirror flip and rotation 
supports two output channels 
speed up to 8mpixels@24fps 
defect pixel correction 
super lens shading correction 
anisotropic non-linear bayer interpolation with false color suppression 
programmable color correction 
advanced contrast enhance and sharping 
advanced saturation adjust 
advanced spatial(2d) de-noise filter 
advanced chrominance noise reduction 
zone-based ae/af/awb statistics 
anti-flick detection statistics 
histogram statistics

audio subsystem 
audio codec

two audio digital-to-analog(dac) channels 
supports analog/digital volume control 
one low-noise analog microphone bias output 
analog low-power loop from microphone to headphone outputs 
supports dynamic range controller adjusting the dac playback output 
one microphone input 
one stereo lineout output 
two audio analog-to-digital(adc) channels

- 92db snr@a-weight 
- supports adc sample rates from 8khz to 48khz
supports automatic gain control(agc) and dynamic range control(drc) adjusting the adc recording input

external peripherals 
 usb

one usb 2.0 otg controller with integrated phy 
complies with usb2.0 specification 
supports high-speed(hs,480 mbit/s),full-speed(fs,12 mbit/s),and low-speed(ls,1.5 mbit/s) in host mode 
complies with enhanced host controller interface (ehci) specification, version 1.0,and the open host controller 
interface(ohci) specification,version 1.0a for host mode 
up to 8 user-configurable endpoints in device mode 
supports point-to-point and point-to-multipoint transfer in both host and peripheral mode

i2s/pcm

compliant with standard inter-ic sound(i2s) bus specification 
compliant with left-justified, right-justified, pcm mode, and tdm(time division multiplexing) format 
full-duplex synchronous work mode 
master and slave mode configured 
adjustable audio sample resolution from 8-bit to 32-bit
sample rate from 8 khz to 192 khz
supports 8-bit u-law and 8-bit a-law companded sample

emac

supports 10/100/1000 mbit/s data transfer rate 
supports rgmii/mii/rmii interface
full-duplex and half-duplex operation 
linked-list descriptor list structure 
programmable frame length to support standard or jumbo ethernet frames with sizes up to 16 kb 
supports a variety of flexible address filtering modes

uart

up to three uart controllers 
64-bytes transmit and receive data fifos for all uart 
compliant with industry-standard 16550 uarts

不直接翻译了，且资料内容太多了，想要看完整的，可参考全志r11 datasheet