STM32F429 >> 22. FMC_扩展外部SDRAM（Code）
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2022-04-01 16:21:32
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本代码用型号为“IS42S16400J”的 SDRAM 芯片为 STM32 扩展内存。
它的行地址宽度为 12 位，列地址宽度为 8 位，内部含有 4 个 Bank，数据线宽度为 16 位，容量大小为8MB。
SDRAM 硬件连接图：
SDRAM 与 STM32 相连的引脚非常多，主要是地址线和数据线。
bsp_sdram.h
/**
******************************************************************************
* @file bsp_sdram.c
* @author Waao
* @version V1.0.0
* @date 24-Feb-2019
* @brief This file contains some board support package's functions for the configuration of the SysTick.
*
******************************************************************************
* @attention
*
* None
*
******************************************************************************
*/
#ifndef __BSP_SDRAM_H_
#define __BSP_SDRAM_H_
#include <stm32f4xx_fmc.h>
#include <stm32f4xx_gpio.h>
#include <bsp_usart.h>
#include <bsp_led.h>
#define IS42S16400J_SIZE 0x800000
#define SDRAM_DEBUG_ON 1
#define SDRAM_INFO(fmt, arg...) printf("<<- SDRAM-INFO ->> "fmt"\n", ##arg)
#define SDRAM_ERROR(fmt, arg...) printf("<<- SDRAM-ERROR ->> "fmt"\n", ##arg)
#define SDRAM_DEBUG(fmt, arg...) do{\
if(SDRAM_DEBUG_ON)\
printf("<<- SDRAM-DEBUG ->> [%d]"fmt"\n", __LINE__, ##arg);\
}\
while(0)
/* Bank selection */
#define FMC_BANK_SDRAM FMC_Bank2_SDRAM
#define FMC_COMMAND_TARGET_BANK FMC_Command_Target_bank2
/* Data BaseAddress */
#define SDRAM_BANK_ADDR ((uint32_t)0xD0000000)
/* Data width */
#define SDRAM_MEMORY_WIDTH FMC_SDMemory_Width_16b
/* SDRAM CAS Latency */
#define SDRAM_CAS_LATENCY FMC_CAS_Latency_2
#define SDCLOCK_PERIOD FMC_SDClock_Period_2 /* Default configuration used with LCD */
#define SDRAM_READBURST FMC_Read_Burst_Enable
/* The relevant definition of FMC SDRAM mode configuring register */
#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
/******************************************************************/
/* A row colunm address signal line */
#define FMC_A0_GPIO_PORT GPIOF
#define FMC_A0_GPIO_CLK RCC_AHB1Periph_GPIOF
#define FMC_A0_GPIO_PIN GPIO_Pin_0
#define FMC_A0_PINSOURCE GPIO_PinSource0
#define FMC_A0_AF GPIO_AF_FMC
#define FMC_A1_GPIO_PORT GPIOF
#define FMC_A1_GPIO_CLK RCC_AHB1Periph_GPIOF
#define FMC_A1_GPIO_PIN GPIO_Pin_1
#define FMC_A1_PINSOURCE GPIO_PinSource1
#define FMC_A1_AF GPIO_AF_FMC
#define FMC_A2_GPIO_PORT GPIOF
#define FMC_A2_GPIO_CLK RCC_AHB1Periph_GPIOF
#define FMC_A2_GPIO_PIN GPIO_Pin_2
#define FMC_A2_PINSOURCE GPIO_PinSource2
#define FMC_A2_AF GPIO_AF_FMC
#define FMC_A3_GPIO_PORT GPIOF
#define FMC_A3_GPIO_CLK RCC_AHB1Periph_GPIOF
#define FMC_A3_GPIO_PIN GPIO_Pin_3
#define FMC_A3_PINSOURCE GPIO_PinSource3
#define FMC_A3_AF GPIO_AF_FMC
#define FMC_A4_GPIO_PORT GPIOF
#define FMC_A4_GPIO_CLK RCC_AHB1Periph_GPIOF
#define FMC_A4_GPIO_PIN GPIO_Pin_4
#define FMC_A4_PINSOURCE GPIO_PinSource4
#define FMC_A4_AF GPIO_AF_FMC
#define FMC_A5_GPIO_PORT GPIOF
#define FMC_A5_GPIO_CLK RCC_AHB1Periph_GPIOF
#define FMC_A5_GPIO_PIN GPIO_Pin_5
#define FMC_A5_PINSOURCE GPIO_PinSource5
#define FMC_A5_AF GPIO_AF_FMC
#define FMC_A6_GPIO_PORT GPIOF
#define FMC_A6_GPIO_CLK RCC_AHB1Periph_GPIOF
#define FMC_A6_GPIO_PIN GPIO_Pin_12
#define FMC_A6_PINSOURCE GPIO_PinSource12
#define FMC_A6_AF GPIO_AF_FMC
#define FMC_A7_GPIO_PORT GPIOF
#define FMC_A7_GPIO_CLK RCC_AHB1Periph_GPIOF
#define FMC_A7_GPIO_PIN GPIO_Pin_13
#define FMC_A7_PINSOURCE GPIO_PinSource13
#define FMC_A7_AF GPIO_AF_FMC
#define FMC_A8_GPIO_PORT GPIOF
#define FMC_A8_GPIO_CLK RCC_AHB1Periph_GPIOF
#define FMC_A8_GPIO_PIN GPIO_Pin_14
#define FMC_A8_PINSOURCE GPIO_PinSource14
#define FMC_A8_AF GPIO_AF_FMC
#define FMC_A9_GPIO_PORT GPIOF
#define FMC_A9_GPIO_CLK RCC_AHB1Periph_GPIOF
#define FMC_A9_GPIO_PIN GPIO_Pin_15
#define FMC_A9_PINSOURCE GPIO_PinSource15
#define FMC_A9_AF GPIO_AF_FMC
#define FMC_A10_GPIO_PORT GPIOG
#define FMC_A10_GPIO_CLK RCC_AHB1Periph_GPIOG
#define FMC_A10_GPIO_PIN GPIO_Pin_0
#define FMC_A10_PINSOURCE GPIO_PinSource0
#define FMC_A10_AF GPIO_AF_FMC
#define FMC_A11_GPIO_PORT GPIOG
#define FMC_A11_GPIO_CLK RCC_AHB1Periph_GPIOG
#define FMC_A11_GPIO_PIN GPIO_Pin_1
#define FMC_A11_PINSOURCE GPIO_PinSource1
#define FMC_A11_AF GPIO_AF_FMC
/* BA address line */
#define FMC_BA0_GPIO_PORT GPIOG
#define FMC_BA0_GPIO_CLK RCC_AHB1Periph_GPIOG
#define FMC_BA0_GPIO_PIN GPIO_Pin_4
#define FMC_BA0_PINSOURCE GPIO_PinSource4
#define FMC_BA0_AF GPIO_AF_FMC
#define FMC_BA1_GPIO_PORT GPIOG
#define FMC_BA1_GPIO_CLK RCC_AHB1Periph_GPIOG
#define FMC_BA1_GPIO_PIN GPIO_Pin_5
#define FMC_BA1_PINSOURCE GPIO_PinSource5
#define FMC_BA1_AF GPIO_AF_FMC
/* DQ data signal line */
#define FMC_D0_GPIO_PORT GPIOD
#define FMC_D0_GPIO_CLK RCC_AHB1Periph_GPIOD
#define FMC_D0_GPIO_PIN GPIO_Pin_14
#define FMC_D0_PINSOURCE GPIO_PinSource14
#define FMC_D0_AF GPIO_AF_FMC
#define FMC_D1_GPIO_PORT GPIOD
#define FMC_D1_GPIO_CLK RCC_AHB1Periph_GPIOD
#define FMC_D1_GPIO_PIN GPIO_Pin_15
#define FMC_D1_PINSOURCE GPIO_PinSource15
#define FMC_D1_AF GPIO_AF_FMC
#define FMC_D2_GPIO_PORT GPIOD
#define FMC_D2_GPIO_CLK RCC_AHB1Periph_GPIOD
#define FMC_D2_GPIO_PIN GPIO_Pin_0
#define FMC_D2_PINSOURCE GPIO_PinSource0
#define FMC_D2_AF GPIO_AF_FMC
#define FMC_D3_GPIO_PORT GPIOD
#define FMC_D3_GPIO_CLK RCC_AHB1Periph_GPIOD
#define FMC_D3_GPIO_PIN GPIO_Pin_1
#define FMC_D3_PINSOURCE GPIO_PinSource1
#define FMC_D3_AF GPIO_AF_FMC
#define FMC_D4_GPIO_PORT GPIOE
#define FMC_D4_GPIO_CLK RCC_AHB1Periph_GPIOE
#define FMC_D4_GPIO_PIN GPIO_Pin_7
#define FMC_D4_PINSOURCE GPIO_PinSource7
#define FMC_D4_AF GPIO_AF_FMC
#define FMC_D5_GPIO_PORT GPIOE
#define FMC_D5_GPIO_CLK RCC_AHB1Periph_GPIOE
#define FMC_D5_GPIO_PIN GPIO_Pin_8
#define FMC_D5_PINSOURCE GPIO_PinSource8
#define FMC_D5_AF GPIO_AF_FMC
#define FMC_D6_GPIO_PORT GPIOE
#define FMC_D6_GPIO_CLK RCC_AHB1Periph_GPIOE
#define FMC_D6_GPIO_PIN GPIO_Pin_9
#define FMC_D6_PINSOURCE GPIO_PinSource9
#define FMC_D6_AF GPIO_AF_FMC
#define FMC_D7_GPIO_PORT GPIOE
#define FMC_D7_GPIO_CLK RCC_AHB1Periph_GPIOE
#define FMC_D7_GPIO_PIN GPIO_Pin_10
#define FMC_D7_PINSOURCE GPIO_PinSource10
#define FMC_D7_AF GPIO_AF_FMC
#define FMC_D8_GPIO_PORT GPIOE
#define FMC_D8_GPIO_CLK RCC_AHB1Periph_GPIOE
#define FMC_D8_GPIO_PIN GPIO_Pin_11
#define FMC_D8_PINSOURCE GPIO_PinSource11
#define FMC_D8_AF GPIO_AF_FMC
#define FMC_D9_GPIO_PORT GPIOE
#define FMC_D9_GPIO_CLK RCC_AHB1Periph_GPIOE
#define FMC_D9_GPIO_PIN GPIO_Pin_12
#define FMC_D9_PINSOURCE GPIO_PinSource12
#define FMC_D9_AF GPIO_AF_FMC
#define FMC_D10_GPIO_PORT GPIOE
#define FMC_D10_GPIO_CLK RCC_AHB1Periph_GPIOE
#define FMC_D10_GPIO_PIN GPIO_Pin_13
#define FMC_D10_PINSOURCE GPIO_PinSource13
#define FMC_D10_AF GPIO_AF_FMC
#define FMC_D11_GPIO_PORT GPIOE
#define FMC_D11_GPIO_CLK RCC_AHB1Periph_GPIOE
#define FMC_D11_GPIO_PIN GPIO_Pin_14
#define FMC_D11_PINSOURCE GPIO_PinSource14
#define FMC_D11_AF GPIO_AF_FMC
#define FMC_D12_GPIO_PORT GPIOE
#define FMC_D12_GPIO_CLK RCC_AHB1Periph_GPIOE
#define FMC_D12_GPIO_PIN GPIO_Pin_15
#define FMC_D12_PINSOURCE GPIO_PinSource15
#define FMC_D12_AF GPIO_AF_FMC
#define FMC_D13_GPIO_PORT GPIOD
#define FMC_D13_GPIO_CLK RCC_AHB1Periph_GPIOD
#define FMC_D13_GPIO_PIN GPIO_Pin_8
#define FMC_D13_PINSOURCE GPIO_PinSource8
#define FMC_D13_AF GPIO_AF_FMC
#define FMC_D14_GPIO_PORT GPIOD
#define FMC_D14_GPIO_CLK RCC_AHB1Periph_GPIOD
#define FMC_D14_GPIO_PIN GPIO_Pin_9
#define FMC_D14_PINSOURCE GPIO_PinSource9
#define FMC_D14_AF GPIO_AF_FMC
#define FMC_D15_GPIO_PORT GPIOD
#define FMC_D15_GPIO_CLK RCC_AHB1Periph_GPIOD
#define FMC_D15_GPIO_PIN GPIO_Pin_10
#define FMC_D15_PINSOURCE GPIO_PinSource10
#define FMC_D15_AF GPIO_AF_FMC
/* Control signal line */
/* CS chip selection */
#define FMC_CS_GPIO_PORT GPIOH
#define FMC_CS_GPIO_CLK RCC_AHB1Periph_GPIOH
#define FMC_CS_GPIO_PIN GPIO_Pin_6
#define FMC_CS_PINSOURCE GPIO_PinSource6
#define FMC_CS_AF GPIO_AF_FMC
/* WE Write enable */
#define FMC_WE_GPIO_PORT GPIOC
#define FMC_WE_GPIO_CLK RCC_AHB1Periph_GPIOC
#define FMC_WE_GPIO_PIN GPIO_Pin_0
#define FMC_WE_PINSOURCE GPIO_PinSource0
#define FMC_WE_AF GPIO_AF_FMC
/* RAS row selection */
#define FMC_RAS_GPIO_PORT GPIOF
#define FMC_RAS_GPIO_CLK RCC_AHB1Periph_GPIOF
#define FMC_RAS_GPIO_PIN GPIO_Pin_11
#define FMC_RAS_PINSOURCE GPIO_PinSource11
#define FMC_RAS_AF GPIO_AF_FMC
/* CAS column selection */
#define FMC_CAS_GPIO_PORT GPIOG
#define FMC_CAS_GPIO_CLK RCC_AHB1Periph_GPIOG
#define FMC_CAS_GPIO_PIN GPIO_Pin_15
#define FMC_CAS_PINSOURCE GPIO_PinSource15
#define FMC_CAS_AF GPIO_AF_FMC
/* CLK synchronous clock, store area 2*/
#define FMC_CLK_GPIO_PORT GPIOG
#define FMC_CLK_GPIO_CLK RCC_AHB1Periph_GPIOG
#define FMC_CLK_GPIO_PIN GPIO_Pin_8
#define FMC_CLK_PINSOURCE GPIO_PinSource8
#define FMC_CLK_AF GPIO_AF_FMC
/* CKE clock enable, store area 2*/
#define FMC_CKE_GPIO_PORT GPIOH
#define FMC_CKE_GPIO_CLK RCC_AHB1Periph_GPIOH
#define FMC_CKE_GPIO_PIN GPIO_Pin_7
#define FMC_CKE_PINSOURCE GPIO_PinSource7
#define FMC_CKE_AF GPIO_AF_FMC
/* DQM1 data mask */
#define FMC_UDQM_GPIO_PORT GPIOE
#define FMC_UDQM_GPIO_CLK RCC_AHB1Periph_GPIOE
#define FMC_UDQM_GPIO_PIN GPIO_Pin_1
#define FMC_UDQM_PINSOURCE GPIO_PinSource1
#define FMC_UDQM_AF GPIO_AF_FMC
/* DQM0 data mask */
#define FMC_LDQM_GPIO_PORT GPIOE
#define FMC_LDQM_GPIO_CLK RCC_AHB1Periph_GPIOE
#define FMC_LDQM_GPIO_PIN GPIO_Pin_0
#define FMC_LDQM_PINSOURCE GPIO_PinSource0
#define FMC_LDQM_AF GPIO_AF_FMC
void SDRAM_GPIO_Config(void);
void SDRAM_InitSequence(void);
void FMC_SDRAM_Config(void);
uint8_t SDRAM_Test(void);
#endif
bsp_sdram.c
/**
******************************************************************************
* @file bsp_sdram.c
* @author Waao
* @version V1.0.0
* @date 24-Feb-2019
* @brief This file contains some board support package's functions for the FMC-SDRAM
*
******************************************************************************
* @attention
*
* None
*
******************************************************************************
*/
#include <bsp_sdram.h>
/**
* @brief Delay.
* @param None
* @retval None
*/
static void SDRAM_Delay(__IO u32 nCount)
{
__IO u32 index = 0;
for(index = (100000 * nCount); index != 0; index--);
}
/**
* @brief Initialize the SDRAM's GPIO.
* @param None
* @retval None
*/
void SDRAM_GPIO_Config(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
/* Address signal line */
RCC_AHB1PeriphClockCmd(FMC_A0_GPIO_CLK | FMC_A1_GPIO_CLK | FMC_A2_GPIO_CLK |
FMC_A3_GPIO_CLK | FMC_A4_GPIO_CLK | FMC_A5_GPIO_CLK |
FMC_A6_GPIO_CLK | FMC_A7_GPIO_CLK | FMC_A8_GPIO_CLK |
FMC_A9_GPIO_CLK | FMC_A10_GPIO_CLK| FMC_A11_GPIO_CLK|
FMC_BA0_GPIO_CLK| FMC_BA1_GPIO_CLK|
/* Data signal line */
FMC_D0_GPIO_CLK | FMC_D1_GPIO_CLK | FMC_D2_GPIO_CLK |
FMC_D3_GPIO_CLK | FMC_D4_GPIO_CLK | FMC_D5_GPIO_CLK |
FMC_D6_GPIO_CLK | FMC_D7_GPIO_CLK | FMC_D8_GPIO_CLK |
FMC_D9_GPIO_CLK | FMC_D10_GPIO_CLK| FMC_D11_GPIO_CLK|
FMC_D12_GPIO_CLK| FMC_D13_GPIO_CLK| FMC_D14_GPIO_CLK|
FMC_D15_GPIO_CLK|
/* Control signal line */
FMC_CS_GPIO_CLK | FMC_WE_GPIO_CLK | FMC_RAS_GPIO_CLK |
FMC_CAS_GPIO_CLK |FMC_CLK_GPIO_CLK | FMC_CKE_GPIO_CLK |
FMC_UDQM_GPIO_CLK|FMC_LDQM_GPIO_CLK, ENABLE);
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
/* A row and column address signal line */
GPIO_InitStructure.GPIO_Pin = FMC_A0_GPIO_PIN;
GPIO_Init(FMC_A0_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_A0_GPIO_PORT, FMC_A0_PINSOURCE , FMC_A0_AF);
GPIO_InitStructure.GPIO_Pin = FMC_A1_GPIO_PIN;
GPIO_Init(FMC_A1_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_A1_GPIO_PORT, FMC_A1_PINSOURCE , FMC_A1_AF);
GPIO_InitStructure.GPIO_Pin = FMC_A2_GPIO_PIN;
GPIO_Init(FMC_A2_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_A2_GPIO_PORT, FMC_A2_PINSOURCE , FMC_A2_AF);
GPIO_InitStructure.GPIO_Pin = FMC_A3_GPIO_PIN;
GPIO_Init(FMC_A3_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_A3_GPIO_PORT, FMC_A3_PINSOURCE , FMC_A3_AF);
GPIO_InitStructure.GPIO_Pin = FMC_A4_GPIO_PIN;
GPIO_Init(FMC_A4_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_A4_GPIO_PORT, FMC_A4_PINSOURCE , FMC_A4_AF);
GPIO_InitStructure.GPIO_Pin = FMC_A5_GPIO_PIN;
GPIO_Init(FMC_A5_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_A5_GPIO_PORT, FMC_A5_PINSOURCE , FMC_A5_AF);
GPIO_InitStructure.GPIO_Pin = FMC_A6_GPIO_PIN;
GPIO_Init(FMC_A6_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_A6_GPIO_PORT, FMC_A6_PINSOURCE , FMC_A6_AF);
GPIO_InitStructure.GPIO_Pin = FMC_A7_GPIO_PIN;
GPIO_Init(FMC_A7_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_A7_GPIO_PORT, FMC_A7_PINSOURCE , FMC_A7_AF);
GPIO_InitStructure.GPIO_Pin = FMC_A8_GPIO_PIN;
GPIO_Init(FMC_A8_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_A8_GPIO_PORT, FMC_A8_PINSOURCE , FMC_A8_AF);
GPIO_InitStructure.GPIO_Pin = FMC_A9_GPIO_PIN;
GPIO_Init(FMC_A9_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_A9_GPIO_PORT, FMC_A9_PINSOURCE , FMC_A9_AF);
GPIO_InitStructure.GPIO_Pin = FMC_A10_GPIO_PIN;
GPIO_Init(FMC_A10_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_A10_GPIO_PORT, FMC_A10_PINSOURCE , FMC_A10_AF);
GPIO_InitStructure.GPIO_Pin = FMC_A11_GPIO_PIN;
GPIO_Init(FMC_A11_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_A11_GPIO_PORT, FMC_A11_PINSOURCE , FMC_A11_AF);
/* BA address signal line */
GPIO_InitStructure.GPIO_Pin = FMC_BA0_GPIO_PIN;
GPIO_Init(FMC_BA0_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_BA0_GPIO_PORT, FMC_BA0_PINSOURCE , FMC_BA0_AF);
GPIO_InitStructure.GPIO_Pin = FMC_BA1_GPIO_PIN;
GPIO_Init(FMC_BA1_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_BA1_GPIO_PORT, FMC_BA1_PINSOURCE , FMC_BA1_AF);
/* DQ data signal line */
GPIO_InitStructure.GPIO_Pin = FMC_D0_GPIO_PIN;
GPIO_Init(FMC_D0_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_D0_GPIO_PORT, FMC_D0_PINSOURCE , FMC_D0_AF);
GPIO_InitStructure.GPIO_Pin = FMC_D1_GPIO_PIN;
GPIO_Init(FMC_D1_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_D1_GPIO_PORT, FMC_D1_PINSOURCE , FMC_D1_AF);
GPIO_InitStructure.GPIO_Pin = FMC_D2_GPIO_PIN;
GPIO_Init(FMC_D2_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_D2_GPIO_PORT, FMC_D2_PINSOURCE , FMC_D2_AF);
GPIO_InitStructure.GPIO_Pin = FMC_D3_GPIO_PIN;
GPIO_Init(FMC_D3_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_D3_GPIO_PORT, FMC_D3_PINSOURCE , FMC_D3_AF);
GPIO_InitStructure.GPIO_Pin = FMC_D4_GPIO_PIN;
GPIO_Init(FMC_D4_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_D4_GPIO_PORT, FMC_D4_PINSOURCE , FMC_D4_AF);
GPIO_InitStructure.GPIO_Pin = FMC_D5_GPIO_PIN;
GPIO_Init(FMC_D5_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_D5_GPIO_PORT, FMC_D5_PINSOURCE , FMC_D5_AF);
GPIO_InitStructure.GPIO_Pin = FMC_D6_GPIO_PIN;
GPIO_Init(FMC_D6_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_D6_GPIO_PORT, FMC_D6_PINSOURCE , FMC_D6_AF);
GPIO_InitStructure.GPIO_Pin = FMC_D7_GPIO_PIN;
GPIO_Init(FMC_D7_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_D7_GPIO_PORT, FMC_D7_PINSOURCE , FMC_D7_AF);
GPIO_InitStructure.GPIO_Pin = FMC_D8_GPIO_PIN;
GPIO_Init(FMC_D8_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_D8_GPIO_PORT, FMC_D8_PINSOURCE , FMC_D8_AF);
GPIO_InitStructure.GPIO_Pin = FMC_D9_GPIO_PIN;
GPIO_Init(FMC_D9_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_D9_GPIO_PORT, FMC_D9_PINSOURCE , FMC_D9_AF);
GPIO_InitStructure.GPIO_Pin = FMC_D10_GPIO_PIN;
GPIO_Init(FMC_D10_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_D10_GPIO_PORT, FMC_D10_PINSOURCE , FMC_D10_AF);
GPIO_InitStructure.GPIO_Pin = FMC_D11_GPIO_PIN;
GPIO_Init(FMC_D11_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_D11_GPIO_PORT, FMC_D11_PINSOURCE , FMC_D11_AF);
GPIO_InitStructure.GPIO_Pin = FMC_D12_GPIO_PIN;
GPIO_Init(FMC_D12_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_D12_GPIO_PORT, FMC_D12_PINSOURCE , FMC_D12_AF);
GPIO_InitStructure.GPIO_Pin = FMC_D13_GPIO_PIN;
GPIO_Init(FMC_D13_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_D13_GPIO_PORT, FMC_D13_PINSOURCE , FMC_D13_AF);
GPIO_InitStructure.GPIO_Pin = FMC_D14_GPIO_PIN;
GPIO_Init(FMC_D14_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_D14_GPIO_PORT, FMC_D14_PINSOURCE , FMC_D14_AF);
GPIO_InitStructure.GPIO_Pin = FMC_D15_GPIO_PIN;
GPIO_Init(FMC_D15_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_D15_GPIO_PORT, FMC_D15_PINSOURCE , FMC_D15_AF);
/* Control signal line */
GPIO_InitStructure.GPIO_Pin = FMC_CS_GPIO_PIN;
GPIO_Init(FMC_CS_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_CS_GPIO_PORT, FMC_CS_PINSOURCE , FMC_CS_AF);
GPIO_InitStructure.GPIO_Pin = FMC_WE_GPIO_PIN;
GPIO_Init(FMC_WE_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_WE_GPIO_PORT, FMC_WE_PINSOURCE , FMC_WE_AF);
GPIO_InitStructure.GPIO_Pin = FMC_RAS_GPIO_PIN;
GPIO_Init(FMC_RAS_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_RAS_GPIO_PORT, FMC_RAS_PINSOURCE , FMC_RAS_AF);
GPIO_InitStructure.GPIO_Pin = FMC_CAS_GPIO_PIN;
GPIO_Init(FMC_CAS_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_CAS_GPIO_PORT, FMC_CAS_PINSOURCE , FMC_CAS_AF);
GPIO_InitStructure.GPIO_Pin = FMC_CLK_GPIO_PIN;
GPIO_Init(FMC_CLK_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_CLK_GPIO_PORT, FMC_CLK_PINSOURCE , FMC_CLK_AF);
GPIO_InitStructure.GPIO_Pin = FMC_CKE_GPIO_PIN;
GPIO_Init(FMC_CKE_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_CKE_GPIO_PORT, FMC_CKE_PINSOURCE , FMC_CKE_AF);
GPIO_InitStructure.GPIO_Pin = FMC_UDQM_GPIO_PIN;
GPIO_Init(FMC_UDQM_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_UDQM_GPIO_PORT, FMC_UDQM_PINSOURCE , FMC_UDQM_AF);
GPIO_InitStructure.GPIO_Pin = FMC_LDQM_GPIO_PIN;
GPIO_Init(FMC_LDQM_GPIO_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(FMC_LDQM_GPIO_PORT, FMC_LDQM_PINSOURCE , FMC_LDQM_AF);
}
/**
* @brief Initialize the SDRAM.
* @param None
* @retval None
*/
void SDRAM_InitSequence(void)
{
u32 TEMP = 0;
FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure;
/* Open the clock */
FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_CLK_Enabled;
FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_COMMAND_TARGET_BANK;
FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 0;
FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
while(FMC_GetFlagStatus(FMC_BANK_SDRAM, FMC_FLAG_Busy) == SET);
FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
SDRAM_Delay(10);
/* Recharge */
FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_PALL;
FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_COMMAND_TARGET_BANK;
FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 0;
FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
while(FMC_GetFlagStatus(FMC_BANK_SDRAM, FMC_FLAG_Busy) == SET);
FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
/* AutoRefresh */
FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_AutoRefresh;
FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_COMMAND_TARGET_BANK;
FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 2;
FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
while(FMC_GetFlagStatus(FMC_BANK_SDRAM, FMC_FLAG_Busy) == SET);
FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
TEMP = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_4 |
SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |
SDRAM_MODEREG_CAS_LATENCY_2 |
SDRAM_MODEREG_OPERATING_MODE_STANDARD |
SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
/* LoadMode */
FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_LoadMode;
FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_COMMAND_TARGET_BANK;
FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = TEMP;
while(FMC_GetFlagStatus(FMC_BANK_SDRAM, FMC_FLAG_Busy) == SET);
FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
/* Set the refresh counter
*/
FMC_SetRefreshCount(1386);
while(FMC_GetFlagStatus(FMC_BANK_SDRAM, FMC_FLAG_Busy) == SET);
}
/**
* @brief Initialize the FMC.
* @param None
* @retval None
*/
void FMC_SDRAM_Config(void)
{
FMC_SDRAMTimingInitTypeDef FMC_SDRAMTiming_InitStructure;
FMC_SDRAMInitTypeDef FMC_SDRAM_InitStructure;
SDRAM_GPIO_Config();
RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE);
/**************** FMC_SDRAMTiming_InitStructure ****************/
/* TMRD: 2 Clock cycles */
FMC_SDRAMTiming_InitStructure.FMC_LoadToActiveDelay = 2;
/* TXSR: min=70ns (7x11.11ns) */
FMC_SDRAMTiming_InitStructure.FMC_ExitSelfRefreshDelay = 7;
/* TRAS: min=42ns (4x11.11ns) max=120k (ns) */
FMC_SDRAMTiming_InitStructure.FMC_SelfRefreshTime = 4;
/* TRC: min=70 (7x11.11ns) */
FMC_SDRAMTiming_InitStructure.FMC_RowCycleDelay = 7;
/* TWR: min=1+ 7ns (1+1x11.11ns) */
FMC_SDRAMTiming_InitStructure.FMC_WriteRecoveryTime = 2;
/* TRP: 15ns => 2x11.11ns */
FMC_SDRAMTiming_InitStructure.FMC_RPDelay = 2;
/* TRCD: 15ns => 2x11.11ns */
FMC_SDRAMTiming_InitStructure.FMC_RCDDelay = 2;
/******************* FMC_SDRAM_InitStructure *******************/
FMC_SDRAM_InitStructure.FMC_Bank = FMC_BANK_SDRAM;
FMC_SDRAM_InitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b;
FMC_SDRAM_InitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_12b;
FMC_SDRAM_InitStructure.FMC_SDMemoryDataWidth = SDRAM_MEMORY_WIDTH;
FMC_SDRAM_InitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4;
FMC_SDRAM_InitStructure.FMC_CASLatency = SDRAM_CAS_LATENCY;
FMC_SDRAM_InitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable;
FMC_SDRAM_InitStructure.FMC_SDClockPeriod = SDCLOCK_PERIOD;
FMC_SDRAM_InitStructure.FMC_ReadBurst = SDRAM_READBURST;
FMC_SDRAM_InitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_0;
FMC_SDRAM_InitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTiming_InitStructure;
FMC_SDRAMInit(&FMC_SDRAM_InitStructure);
SDRAM_InitSequence();
}
/**
* @brief Check if the SDRAM was damaged.
* @param None
* @retval None
*/
uint8_t SDRAM_Test(void)
{
uint32_t counter = 0;
uint8_t ubWritedata_8b = 0, ubReaddata_8b = 0;
uint16_t uhWritedata_16b = 0, uhReaddata_16b = 0;
SDRAM_INFO("Now is detecting the SDRAM, read and write with the way of 8 bits and 16 bits...");
/******* Read and Write with the way of 8 bits, and check *******/
/* Reset all the SDRAM data to 0x00 */
for(counter = 0; counter < IS42S16400J_SIZE; counter++)
{
*(__IO uint8_t*)(SDRAM_BANK_ADDR + counter) = (uint8_t)0x00;
}
/* Write the data to SDRAM */
for(counter = 0x00; counter < IS42S16400J_SIZE; counter++)
{
*(__IO uint8_t*)(SDRAM_BANK_ADDR + counter) = (uint8_t)(ubWritedata_8b + counter);
}
/**/
for(counter = 0; counter < IS42S16400J_SIZE; counter++)
{
ubReaddata_8b = *(__IO uint8_t*)(SDRAM_BANK_ADDR + counter);
if(ubReaddata_8b != (uint8_t)(ubWritedata_8b + counter))
{
SDRAM_ERROR("The 8-bits data is not match.");
printf("\nThe error place is %d and error data is %d and %d", counter, ubReaddata_8b, (uint8_t)(ubWritedata_8b + counter));
return 0;
}
}
/******* Read and Write with the way of 16 bits, and check *******/
for(counter = 0; counter < IS42S16400J_SIZE/2; counter++)
{
*(__IO uint16_t*)(SDRAM_BANK_ADDR + 2*counter) = (uint16_t)0x00;
}
for(counter = 0; counter < IS42S16400J_SIZE/2; counter++)
{
*(__IO uint16_t*)(SDRAM_BANK_ADDR + 2*counter) = (uint16_t)(uhWritedata_16b + counter);
}
for(counter = 0; counter < IS42S16400J_SIZE/2; counter++)
{
uhReaddata_16b = *(__IO uint16_t*)(SDRAM_BANK_ADDR + 2*counter);
if(uhReaddata_16b != (uint16_t)(uhWritedata_16b + counter))
{
SDRAM_ERROR("The 16-bits data is not match.");
printf("\nThe error place is %d and error data is %d and %d", counter, uhReaddata_16b, (uint16_t)(uhWritedata_16b + counter));
return 0;
}
}
SDRAM_INFO("The test is successful !");
return 1;
}
main.c
/**
******************************************************************************
* @file main.c
* @author Waao
* @version V1.0.0
* @date 24-Feb-2019
* @brief MAIN.
* On this project, you can configure the SDRAM through the FMC peripheral
* and check if it works properly
*
******************************************************************************
* @attention
*
* None
*
******************************************************************************
*/
#include <bsp_sdram.h>
#include <bsp_systick.h>
#include <bsp_led.h>
#include <bsp_usart.h>
#include <bsp_led.h>
int main(void)
{
USART1_Config();
LED_GPIO_Config();
printf("\nThe test is begin.");
FMC_SDRAM_Config();
if(SDRAM_Test() == 1)
{
LED_GREEN;
}
else
{
LED_RED;
}
/******* Access the SDRAM using the pointer *******/
{
uint32_t TEMP;
printf("\n\nAccess the SDRAM using the pointer.");
*( uint8_t*) (SDRAM_BANK_ADDR ) = (uint8_t)0xAA;
TEMP = *(uint8_t*)(SDRAM_BANK_ADDR);
printf("\nThe data what you get is 0x%X", TEMP);
*( uint16_t*)(SDRAM_BANK_ADDR+1) = (uint16_t)0xBBBB;
TEMP = *( uint16_t*)(SDRAM_BANK_ADDR+1);
printf("\nThe data what you get is 0x%X", TEMP);
}
}
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