数字IC基础知识1
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2022-03-26 21:52:58
IC芯片设计流程步骤工具/相关内容人员Marketing Request (市场需求)Architecture spec（架构说明书 ）Top architectArchitecture engineerArch/Algorithm Emulation （架构/算法仿真）C/C++/MatlabAlgorithm EngineerDesign Spec（设计说明书）Design Spec exampleRTL Coding（RTL代码）VH...
IC芯片设计流程
| 步骤 | 工具/相关内容 | 人员 |
|---|---|---|
| Marketing Request (市场需求) | ||
| Architecture spec（架构说明书 ） | Top architect | Architecture engineer |
| Arch/Algorithm Emulation （架构/算法仿真） | C/C++/Matlab | Algorithm Engineer |
| Design Spec（设计说明书） | Design Spec example | |
| RTL Coding（RTL代码） | VHDL/Verilog/SystemVerilog | RTL design engineer/design engineer |
| IP Level RTL coding | ||
| IP Level RTL simulation | Makefile 仿真验证工具:cadence：Incisive. Synopsys: VCS. Mentor:Questasim. | |
| ( IP Level verification ) | C/C++/SystemC/SystemVerilog /UVM | verification Spec/ test plan |
| unit / chip Level RTL simulation | ||
| （ unit / chip Level RTL verification ） | full _chip test plan | full chip verification engineer |
| Logic Synthesis | 逻辑综合工具：Cadence：Genus. Synopsys:Design Compile(DC) | ASIC Design Engineer |
| (Gate Level verification) | Gate Level verification Engineer | |
| 形式验证 | 形式验证工具：Cadence：Conformal.Synopsys: Formality | ASIC Front-End design engineer |
| STA | TCL Script 静态时序分析工具：Cadence：Temus. Synopsys: PrimeTime （PT). STA timing满足，得到最终Netlist | ASIC Front-End design engineer |
| DFT(design for test) | 插入可测试链 scan chain | DFT engineer |
| 版图生成，自动布局布线（PR,place and route） | 工具：Cadence ：innovus. Synopsys: IC Compiler (ICC) | physical design engineer |
| 时钟树插入 | ||
| DRC/LVS | 物理验证工具：Mentor：Calibre . Synopsys: Hercules. Cadence :Diva/dracura | LVS:layout versus schematic，版图电路一致性检查；DRC:design rule check，设计规则检查。 |
| Post_Layout STA | ||
| 生成最终GDSII | ||
| Tap-Out 流片 |
SOC芯片架构图
各个模块内容：
该芯片的应用场景
本文地址：https://blog.csdn.net/qq_41381140/article/details/110871186