嵌入式linux开发 (十) RAM(4) I.MX6ULL外扩DDR3L

- 正点原子ARMLinux开发板 I.MX6ULL	cortex-A7
	-外扩
		NT5CC256M16EP-EK:512MB,DDR3L

• soc

The i.MX 6ULL application processors are NXP's latest additions to a growing family of real-time processing products offering high-performance processing optimized for lowest power consumption.
The i.MX 6ULL processors feature NXP's advanced implementation of the ARM ® Cortex ® -A7 core.
The processors can be interfaced with DDR3, DDR3L LPDDR2 (single channel) DRAM memory devices.


This chip has these external memory interfaces and controllers:
• Multi-Mode DDR Controller (MMDC)
	8000_0000 FFFF_FFFF 2048 MB MMDC—x16 DDR Controller.
• EIM-PSRAM/NOR flash controller
	The EIM block provides an interface for SRAM and PSRAM, and a 16/8-bit NOR flash.
	All EIM pins are muxed on other interfaces.
	5000_0000 57FF_FFFF 128 MB EIM (NOR/SRAM)

SOC端 内存控制器

• 总介

MMDC is a multi-mode DDR controller that supports DDR3/DDR3L x16 and LPDDR2x16 memory types. 
MMDC is configurable, high performance, and optimized.
					

• 寄存器及映射

基地址:0x0021B0000 开始的 80 个寄存器,一个寄存器4个字节
0000-0040 : 16个
0400-0400 : 16个
0800-08C0 : 48个

• 引脚

Signal 				Description 			
------------------------- sclk
DRAM_SDCKE[1:0] 	Clock Enable Signals 
DRAM_SDCLK0_N 		Negative Clock Signals 	
DRAM_SDCLK0_P 		Positive Clock Signals 	
------------------------- data and addr
DRAM_ADDR[15:0] 	Address Bus Signals
DRAM_DATA[31:0] 	Data Bus Signals 		
------------------------- bank select
DRAM_SDBA[2:0] 		Bank Select Signals
------------------------- control
DRAM_CS[1:0] 		Chip Selects

DRAM_CAS 			Column Address Strobe Signal
DRAM_RAS 			Row Address Strobe Signal 

DRAM_SDWE 			WE signal

DRAM_DQM[1:0] 		Data Mask Signals  

-------------------以下为较SDDRAM控制器新增------------------------------------------------------------------
------------------------- ???
DRAM_ODT[1:0] 		On-Die Termination Signals 
				
DRAM_SDQS[1:0]_N 	Negative DQS Signals 			
DRAM_SDQS[1:0]_P 	Positive DQS Signals


------------------------- 接地
DRAM_RESET 			Reset Signal 				
DRAM_ZQPAD 			ZQ signal 	

• 时序

设备端 DDR3L芯片(NT5CC256M16EP-EK)

• 引脚
• 时序

连线

代码

• 初始化

• 读写内存