DAC7744 FPGA控制 实际产品拷机测试过

	`timescale 1ns / 1ps
	//-----------------------------------------------------------
	module DAC_CTRL(
	input FCLK_50M,
	input rst_n,
	input [15:0] dac_dataout,
	output reg [1:0] DAC_ADR,
	output reg DAC_LOAD,
	output DAC_RST,
	output reg DAC_CS_N,
	output reg [15:0] DAC_DAT,
	//
	input [15:0] dac_value1,
	input [15:0] dac_value2,
	input [15:0] dac_value3,
	input [15:0] dac_value4
	);
	 
	//-----------------------------------------------------------
	//posedge is active for reset.
	assign DAC_RST = rst_n;
	//-----------------------------------------------------------
	
	
	//-----------------------------------------------------------
	reg [5:0] wr_state;
	always @(posedge FCLK_50M)
	begin
		if(~rst_n) wr_state <= 6'b0;
		else wr_state <= wr_state + 1;
	end
	//
	always @(posedge FCLK_50M)
	begin
		if(~rst_n) DAC_CS_N <= 1'b1;
		else
			begin
			case(wr_state)
			6'd1 :	begin 
						DAC_CS_N <= 1'b0 ; 
						DAC_ADR <= 2'b00; 
						DAC_LOAD