好玩的modelsim波形仿真显示汉字

先上效果图

verilog代码

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 07:08:29 03/06/2020
// Design Name:
// Module Name: gen_line
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module gen_line
#(
parameter COL_CNT = 16’d80,
parameter TURN = 1’b1
)
(
input [127:0]row_data,
output odata,

input bit_clk,       //100ns

input bit1_roll_clk, //2ns
input reset_p
);
reg [15:0]col_cnt;
wire odata_temp;

[e-mail](posedge bit_clk or posedge reset_p)
begin
if(reset_p)
col_cnt <= 16’d0;
else if(col_cnt == COL_CNT-1)
col_cnt <= COL_CNT - 1’d1;
else
col_cnt <= col_cnt + 1’d1;
end

assign odata_temp_p = row_data[COL_CNT - 1 - col_cnt] ? bit1_roll_clk : 1’d1;
assign odata_temp_n = row_data[COL_CNT - 1 - col_cnt] ? 1’d1 : bit1_roll_clk;

assign odata = TURN ? odata_temp_n : odata_temp_p;

endmodule

测试文件代码

`timescale 1ns/1ns

module sim_char_display();
wire [15:0]odata;
reg [63:0]data1_row[15:0];
reg [63:0]data2_row[15:0];

reg bit_clk;
reg bit1_roll_clk;
reg reset_p;

initial bit_clk = 1'b1;
always #50 bit_clk = ~bit_clk;

initial bit1_roll_clk = 1'b1;
always #1 bit1_roll_clk = ~bit1_roll_clk;


initial begin
  data1_row[15] = 64'h0020020022080000 ;
  data1_row[14] = 64'h3FF0010011080004;
  data1_row[13] = 64'h020000801110FFFE ;
  data1_row[12] = 64'h020000C000200004 ;
  data1_row[11] = 64'h020008807FFE0804 ;
  data1_row[10] = 64'h0208080040020404;
  data1_row[9 ] = 64'h7FFC280880040204 ;
  data1_row[8 ] = 64'h028028041FE00224 ;
  data1_row[7 ] = 64'h02802802004000C4 ;
  data1_row[6 ] = 64'h0480480201840304 ;
  data1_row[5 ] = 64'h04808802FFFE0C04;
  data1_row[4 ] = 64'h0880080001003004 ;
  data1_row[3 ] = 64'h0882081001001004 ;
  data1_row[2 ] = 64'h1082081001000044 ;
  data1_row[1 ] = 64'h207E07F005000028;
  data1_row[0 ] = 64'h4000000002000010 ;
end               




  //reset
  initial begin
    reset_p = 1'b1;
    #200
    reset_p = 1'b0; 

    #8000
    $stop;    
  end

generate
  genvar i;
  for(i=0;i<16;i=i+1)
  begin:gen_line_data1
    gen_line #(64,0)gen_line0(data1_row[i],odata[i],bit_clk,bit1_roll_clk,reset_p);
  end
endgenerate

endmodule

如果想修改显示的字，只需修改sim_char_display模块中数据代码，这些数据是通过取模软件生成的数据。我这里是在网上下载的一个字符取模软件，这里放一个取模软件生成的数据和点阵显示效果图。
使用的是16x16的点阵，对于这4个字，一行有64个点，共16行，使用16个64bit数据就可以表示这些字符数据。sim_char_display模块中第20行代码就是每个字符对应的第1，2个数据，第21行代码就是每个字符对应的第3，4个数据，以此类推，对想显示的数据进行修改。
除此之外，还有个地方需要对应的做修改和设置，sim_char_display模块中代码55行，在进行gen_line例化时需要注意例化参数的修改。gen_line中参数COL_CNT是设置一行显示的字的个数*16。TURN参数是设置显示效果，COL_CNT设置为1效果是绿底黑字，设置为0效果是黑底绿字。

取模软件导出的数据一般两个16进制数为一个数据，如下：

/* GB2312 16x16点阵字库*/
/* 字串 啊啊啊啊   64x16  */
0x00,0x04,0x00,0x04,0x00,0x04,0x00,0x04,0x2F,0x7E,0x2F,0x7E,0x2F,0x7E,0x2F,0x7E,
0xF9,0x04,0xF9,0x04,0xF9,0x04,0xF9,0x04,0xA9,0x04,0xA9,0x04,0xA9,0x04,0xA9,0x04,
0xAA,0x14,0xAA,0x14,0xAA,0x14,0xAA,0x14,0xAA,0x7C,0xAA,0x7C,0xAA,0x7C,0xAA,0x7C,
0xAC,0x54,0xAC,0x54,0xAC,0x54,0xAC,0x54,0xAA,0x54,0xAA,0x54,0xAA,0x54,0xAA,0x54,
0xAA,0x54,0xAA,0x54,0xAA,0x54,0xAA,0x54,0xA9,0x54,0xA9,0x54,0xA9,0x54,0xA9,0x54,
0xE9,0x74,0xE9,0x74,0xE9,0x74,0xE9,0x74,0xAD,0x54,0xAD,0x54,0xAD,0x54,0xAD,0x54,
0x0A,0x04,0x0A,0x04,0x0A,0x04,0x0A,0x04,0x08,0x04,0x08,0x04,0x08,0x04,0x08,0x04,
0x08,0x14,0x08,0x14,0x08,0x14,0x08,0x14,0x08,0x0C,0x08,0x0C,0x08,0x0C,0x08,0x0C,

这里每行64个16进制数，共8行，每行的数据实际是显示时的两行，我们可以在word里截断为两行，然后将0x和 ， 替换为空，
就会如下显示，便于我们复制粘贴到代码中：
0020020022080000
3FF0010011080004
020000801110FFFE
020000C000200004
020008807FFE0804
0208080040020404
7FFC280880040204
028028041FE00224
02802802004000C4
0480480201840304
04808802FFFE0C04
0880080001003004
0882081001001004
1082081001000044
207E07F005000028
4000000002000010
附一取模软件：https://download.csdn.net/download/weixin_44884357/12230992