Python + FPGA 实现任意波形发生器

PC端

python 代码，通过串口发送至下位机

feq=30000   #Hz
slow_VS_fast=20

print(' DAC data sending...')
ser = serial.Serial('com10',57600,bytesize=8, parity='N', stopbits=1, timeout=None, xonxoff=0, rtscts=0)

PLL=50e6    #Hz
div=1
points=round(PLL/feq/div)
while points >256:
    div+=1
    points=int(round(PLL/feq/div))

cospoints = points

buf=bytearray(cospoints+5)
buf[0]=div-1
buf[1]=(slow_VS_fast*div-1)%256
buf[2]=(slow_VS_fast*div-1)/256
buf[3]=points-1
buf[4]=1
for i in range(0,cospoints):
    buf[i+5]=int(round((math.cos(math.pi*2*i/cospoints)+1)*0.15*127))
    #buf[0]=i   
ser.write(buf)
    # print(buf)    

time.sleep(0.1)


buf[4]=2
for i in range(0,cospoints):
    buf[i+5]=int(round((math.cos(math.pi*2*i/cospoints)+1)*0.35*127))
    #buf[i+5]=0#int(i/2*0.4)
ser.write(buf)


time.sleep(0.1)
ser.close()

FPGA 端 verilog 数据解析如下，

case (command_addr) 
    0:
    begin
        div_max <= spi_rdata;
        command_addr <= 1;
    end
    1:
    begin
        div_max1[7:0] <= spi_rdata;
        command_addr <= 2;                  
    end
    2:
    begin
        div_max1[15:8] <= spi_rdata;
        command_addr <= 3;                  
    end
    3:
    begin
        rd_max <= spi_rdata;
        command_addr <= 13;                 
    end
    13:
    begin
        next_mem_in_addr <= 0;
        next_mem_in_addr1 <= 0;
        if(spi_rdata==8'd1) command_addr <= 14;
        if(spi_rdata==8'd2) command_addr <= 15;
    end
    14:
    begin
        next_mem_in_addr <= next_mem_in_addr + 1;
        mem_in_we <= 1;
    end
    15:
    begin
        next_mem_in_addr1 <= next_mem_in_addr1 + 1;
        mem_in_we1 <= 1;
    end
endcase

附上上述代码的示波器测试图：快波约29.16K（feq），1个慢波周期包含20个（slow_VS_fast）快波