边沿检测电路及代码

//边沿检测
module cy4(
   input signal,
   input clk,
   input rst_n,
   output nege_dge,
   output pose_dge
   );
reg reg_0,reg_1,reg_2;
always @(posedge clk or negedge rst_n)
if(!rst_n)
  begin
    reg_0 <= 0;
    reg_1 <= 0;
    reg_2 <= 0;
  end
else
  begin
    reg_0 <= signal;
    reg_1 <= reg_0;
    reg_2 <= reg_1;
  end
assign nege_dge = ~reg_1 & reg_2;
assign pose_dge = ~reg_2 & reg_1;

endmodule

测试脚本代码：

`timescale 1 ns/ 1 ps
module cy4_vlg_tst();

reg eachvec;
// test vector input registers
reg clk;
reg rst_n;
reg signal;
wire nege_dge;
wire pose_dge;
cy4 i1 (

.clk(clk),
.nege_dge(nege_dge),
.pose_dge(pose_dge),
.rst_n(rst_n),
.signal(signal)

);
initial
begin
clk = 0;
rst_n = 0;
signal = 0;

100;

rst_n = 1;

signal = 1;

100;

stop;$stop;$display(“Running testbench”);
end
always #200 clk = ~clk;
endmodule