FPGA axi-quad-spi IP核寄存器说明

40：(SRR) IP核复位寄存器
写入0000_000A复位

60：(SPICR) SPI控制寄存器
Default Value：0x180

[31:10]	Reserved

[9:9]	(LSB First)

		0 = MSB first transfer format.	1 = LSB first transfer format.

[8:8]	(Master Transaction Inhibit)

		0 = Master transactions enabled.	1 = Master transactions disabled.

[7:7]	(Manual Slave Select Assertion Enable)

		0 = Slave select output asserted by master core logic.
		1 = Slave select output follows data in slave select register.

[6:6]	(RX FIFO Reset)

		0 = Receive FIFO normal operation.		1 = Reset receive FIFO pointer.

[5:5]	(TX FIFO Reset)

		0 = Transmit FIFO normal operation.	1 = Reset transmit FIFO pointer.

[4:4]	(CPHA)	Clock phase:(时钟相位)

		时钟相位是指数据的采样的时刻，决定MOSI或MISO数据线上的信号将会在SCK时钟线的"奇数边沿"被采样或者数据线在SCK的"偶数边沿"采样。

[3:3]	(CPOL)	Clock polarity:(时钟极性)

		时钟极性是指SPI通讯设备处于空闲状态时，SCK信号线的电平信号(即SPI通讯开始前、 CS线为高电平时SCK的状态)。

		0 = Active-High clock; SCK idles Low.	1 = Active-Low clock; SCK idles High.

[2:2]	(Master)	Master (SPI master mode)

		0 = Slave configuration.	1 = Master configuration.

[1:1]	(SPE)	SPI system enable

		0 = SPI system disabled.	1 = SPI system enabled.

[0:0]	(LOOP)	Local loopback mode

		0 = Normal operation.		1 = Loopback mode.

64：(SPISR) SPI状态寄存器 Default Value：0x0a5

68：(SPI DTR) 数据发送寄存器

6C：(SPI DRR) 数据接收寄存器

70：(SPISSR) 从机选择寄存器

[0:0]	0从机选通

		0 = 选通0号从机.		1 = 断开0号从机.

74：(SPI Transmit FIFO Occupancy Registe) 发送FIFO占用寄存器

78：(SPI Receive FIFO Occupancy Register) 接收FIFO占用寄存器

1C：(DGIER) 设备全局中断使能

[31:31]	(GIE)	Global Interrupt Enable.

		0 = Disabled.		1 = Enabled.

20：(IPISR) IP核状态寄存器

[8:8]	(DRR_Not_Empty)	

1 =  the DRR FIFO receives the first data value during the SPI transaction.

[4:4]	(DRR Full)	Data receive register/FIFO full.

1 = the end of the SPI element transfer.

[2:2]	(DTR Empty)		Data transmit register/FIFO empty.

1 = the last byte of data has been transferred out to the external flash memory.

28：(IPIER) IP核中断使能

[8:8]	(DRR_Not_Empty)	

0 = Disabled.		1 = Enabled.

[4:4]	(DRR Full)	Data receive register/FIFO full.

0 = Disabled.		1 = Enabled.

[2:2]	(DTR Empty)		Data transmit register/FIFO empty.

0 = Disabled.		1 = Enabled.