FPGA设计过程中的心得总结与经验

一、跨时钟域处理

在进行FPGA设计过程中，经常会遇到跨时钟域问题，若由快时钟域向慢时钟域进行转换时，需先把快时钟域的信号进行拉长处理，再进行慢时钟域的跨越，处理方法如下：

usr_clk_w 频率 > sclk 频率

reg f_start = 0;

reg [2:0] f_start_cnt;


always @(posedge usr_clk_w)

begin

    if(frame_start)

        f_start <= 1;

    else if(f_start_cnt == 3'd3)

        f_start <= 0;

    else

        f_start <= f_start;

end


always @(posedge usr_clk_w)

begin

    if(frame_start)

        f_start_cnt <= 0;

    else if(f_start_cnt == 3'd3)

        f_start_cnt <= 0;

    else if(f_start)

        f_start_cnt <= f_start_cnt + 1;

    else

        f_start_cnt <= f_start_cnt;

end



reg f_start_dly1;

reg f_start_dly2;

wire  fs_start;

always @(posedge sclk)

begin

    f_start_dly1 <= f_start;

    f_start_dly2 <= f_start_dly1;

end
      
assign  fs_start =   f_start_dly1 && (!f_start_dly2);