EPWM-CMPSS(模拟比较器)模块学习

CMPSS框图：

1. CMPSS的数字滤波器Digital Filter

图1.1

Digital Filter在CMPSS模块中的位置：

Digital Filter 实现的等效C代码如下:

//Equivalent C code of the filter implementation 
//is shown below:
if (FILTER_OUTPUT == 0) {
	if (Num_1s_in_SAMPWIN >= THRESH) {
		FILTER_OUTPUT = 1;
	}
}
else {
	if (Num_0s_in_SAMPWIN >= THRESH) {
		FILTER_OUTPUT = 0;
	}
}

Digital Filter 使用步骤：

1. Configure and enable the comparator for operation
2. Configure the digital filter parameters for operation
   • Set SAMPWIN for the number of samples to monitor in the FIFO window
   • Set THRESH for the threshold required for majority qualification
   • Set CLKPRESCALE for the digital filter clock prescale value
3. Initialize the sample values in the digital FIFO window by setting FILINIT
   //通过设置FILINIT初始化在过滤器窗口中的采样值
4. Clear COMPSTS latch via COMPSTSCLR if the latched path is desired
   //如果需要锁存路径，则通过COMPSTSCLR清除锁存器
5. Configure the CTRIP and CTRIPOUT signal paths
6. If desired, configure the ePWM and GPIO modules to accept the filtered signals

程序配置示例：

#include "F28x_Project.h" 
//参照上述的Digital Filter使用步骤
void InitCMPSS(void)
{
	EALLOW;
	//1. Enable CMPSS
	Cmpss1Regs.COMPCTL.bit.COMPDACE = 1;//1. 使能CMPSS
	//2. Configure the digital filter parameters 配置过滤器参数
		//2.1 设置SAMPWIN
		Cmpss1Regs.CTRIPHFILCTL.bit.SAMPWIN = 0x1F;
		//2.2 设置THRESH 
	    //Maximum THRESH value requires static value for entire window
	    //  THRESH should be GREATER than half of SAMPWIN
	    Cmpss1Regs.CTRIPHFILCTL.bit.THRESH = 0x1F;
		//2.3 设置CLKPRESCALE 
		Cmpss1Regs.CTRIPHFILCLKCTL.bit.CLKPRESCALE = 0x3FF;
	
	//3. Initialize the sample values in the digital FIFO window by setting FILINIT
	//Reset filter logic & start filtering
	Cmpss1Regs.CTRIPHFILCTL.bit.FILINIT = 1;
	//4. Clear COMPSTS latch via COMPSTSCLR if the latched path is desired
	// 通过COMPSTSCLR寄存器清除比较器的状态，按实际情况考虑是否需要
	//5. Configure the CTRIP and CTRIPOUT signal paths 配置CTRIP和CTRIPOUT信号路径
	// Configure CTRIPOUT path
	// Digital filter output feeds CTRIPH and CTRIPOUTH
	Cmpss1Regs.COMPCTL.bit.CTRIPHSEL = CTRIP_FILTER;//配置CMPSS的CTRIPH输出方式 为过滤器输出
	Cmpss1Regs.COMPCTL.bit.CTRIPOUTHSEL = CTRIP_FILTER;//配置CMPSS的CTRIPOUTH输出方式 为过滤器方式输出
	//6. If desired, configure the ePWM and GPIO modules to accept the filtered signals
	// Configure GPIO14 to output CTRIPOUT1H
	GPIO_SetupPinMux(GPIO_PIN_NUM, GPIO_MUX_CPU1, GPIO_PER_NUM);
    // Configure CTRIPOUTH output pin
    // Configure OUTPUTXBAR3 to be CTRIPOUT1H
    OutputXbarRegs.OUTPUT3MUX0TO15CFG.all &= ~((Uint32)1);
    //Enable OUTPUTXBAR3 Mux for Output
    OutputXbarRegs.OUTPUT3MUXENABLE.all |= (Uint32)1;
	
	EDIS;
}

步骤4示意图：

步骤5示意图【仅针对上述示例】：

Digital Filter时钟设置：

Digital Filter时钟寄存器配置：

// Configure Digital Filter
//Maximum CLKPRESCALE value provides the most time between samples
//CTRIPHFILCLKCTL: CTRIPH Filter Clock Control Register  过滤器时钟控制寄存器
Cmpss1Regs.CTRIPHFILCLKCTL.bit.CLKPRESCALE = 0x3FF;//CLKPRESCALE：Sample Clock Prescale

待解决问题：

1. 在程序配置的第6步中【不是很理解】：

配置CMPSS的输出管脚路由：

	// Configure CTRIPOUTH output pin
    // Configure OUTPUTXBAR3 to be CTRIPOUT1H
    OutputXbarRegs.OUTPUT3MUX0TO15CFG.all &= ~((Uint32)1);
    //Enable OUTPUTXBAR3 Mux for Output
    OutputXbarRegs.OUTPUT3MUXENABLE.all |= (Uint32)1;

分析：我看的例程中目标是想将OUPUT X-BAR最终配置到GPIO14上
OUTPUT3MUX0TO15CFG寄存器对应的结构体定义:

GPIO14管脚复用图：

2. 时钟设置值要怎么理解：

Cmpss1Regs.CTRIPHFILCLKCTL.bit.CLKPRESCALE = 0x3FF;