inout端口示例

要实现输入输出的管脚复用,在RTL Viewer中产生下图中红色加粗的器件，Verilog怎么描述呢？

其示例代码如下：

module bidirec (oe, clk, inp, outp, bidir);

// Port Declaration

input   oe;
input   clk;
input   [7:0] inp;
output  [7:0] outp;
inout   [7:0] bidir;

reg     [7:0] a;
reg     [7:0] b;

assign bidir = oe ? a : 8'bZ ;
assign outp  = b;

// Always Construct

always @ (posedge clk)
begin
    b <= bidir;
    a <= inp;
end

endmodule

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参考链接：https://blog.csdn.net/qimoDIY/article/details/99519624